1. Field of the Invention
The present invention relates to a time constant circuit that outputs voltages attenuating as the time passes, and a switch circuit and the like provided with the same.
2. Description of the Related Art
Recently, due to implementation of higher-resolution and larger-scaled panels of display devices, the power consumption within the display devices tend to increase accordingly. In order to stably supply a supply voltage steadily and to stably supply the supply voltage in response to a transient current, it is essential to provide a capacitor for accumulating electric charges and discharging the charges as necessary.
In the meantime, when the capacity of the capacitor is increased to acquire a stable supply voltage, a large rush current is generated at the time of starting up the power supply. This issue becomes more prominent when the resolution and the size of the display devices are increased further.
Japanese Unexamined Patent Publication 2003-111460 (FIG. 1: Patent Document 1) discloses a time constant circuit that controls such rush current. The time constant circuit is structured by disposing a single capacitor and a single resistor in parallel between a gate and a source of an FET (Field Effect Transistor), and disposing a resistor between a gate and a ground (GND) of the FET (see FIG. 8). Through moderating a change in a gate potential of the FET at the time of starting up the FET by the time constant circuit, the rush current is decreased. Between the gate and GND of the FET, a voltage-dividing resistor for determining the gate potential of the FET is disposed.
Further, Japanese Unexamined Patent Publication 2005-223804 (FIG. 4: Patent Document 2) discloses a voltage control circuit that controls the voltage between the gate and the source of the FET. This voltage control circuit uses an operation amplifier, a resistor, and a capacitor for decreasing the rush current. The voltage between the gate and the source of the FET is controlled by the voltage control circuit to decrease the rush current at the time of starting up the FET.
Various kinds of ICs such as a driver IC (Integrated Circuit) for driving the display device and a timing controller require a power source that outputs different voltage values. However, it is desired for the voltage inputted from an external power source to be a single kind of voltage value because it is easy to use. Thus, a power source circuit (DC (Direct Current)/DC converter) that generates a plurality of voltage values from the one kind of voltage value is used. For the output timings of each voltage generated by the DC/DC converter, it is necessary to set the starting order (power source sequence) for avoiding breakdowns and malfunctions of the various kinds of ICs. The starting order is controlled normally by using a component or a device having a switch function such as an FET.
In a case where there is a smoothing capacitor on the output side of the FET when the FET is started up (FET is ON), a large current (rush current) transitionally flows immediately after the FET is turned ON due to a steep charging operation done to the capacitor. When this rush current is too large, the FET may be damaged and the protecting function of the input power source line may malfunction. Even if it does not lead to the malfunctions of the protecting function of the input power source line, an unexpected decrease in the voltage (voltage drop) of the input voltage may occur, and the protecting function of the DC/DC converter may malfunction due to the voltage drop.
In order to reduce the rush current, a change in the voltage between the gate and the source of the FET after the voltage is applied to the FET may be controlled so that the FET starts up gradually. For example, as disclosed in Patent Document 2, a voltage control circuit may be provided between the gate and the source of the FET.
However, in order to properly control the voltage between the gate and the source of the FET by using the voltage control circuit, there is such a shortcoming that the circuit scale is increased. That is, with the structure of Patent Document 2, one operation amplifier, one transistor, one capacitor, and seven resistors are required, so that the circuit scale becomes extremely large. When the circuit scale is increased, the area of the substrate on which the circuit is loaded becomes large. Therefore, the cost as a whole is increased.
Thus, in order to decrease the rush current with a simple structure (only with a passive element), the FET is gradually started up in many cases by providing a time constant circuit that is formed with one resistor and one capacitor between the gate and the source of the FET as disclosed in Patent Document 1 (see FIG. 8).
However, it is necessary to set the value of the time constant determined according to the resistance value of the resistor and the capacitance value of the capacitor to a large value for sufficiently reducing the rush current. When the time constant is increased, however, the time from the point at which the voltage of the FET is applied to the point at which the actually the FET starts up becomes extended. That is, there is such a new issue generated that the start point of the output voltage of the DC/DC converter is delayed. This means that the start timing of the power source that supplies the voltages to the various kinds of ICs is delayed in the display device that is provided with the DC/DC converter. As a result, the time until the various kinds of ICs are driven becomes extended, so that the time from the point at which the power is turned on to the point at which a video is displayed becomes longer.
As described, when the starting timing of the FET is moderated by the time constant circuit to reduce the rush current as much as possible without increasing the circuit scale, the rush current can be decreased. However, there is generated another issue that the starting timing becomes delayed. When the starting timing is delayed, the time until an image displayed becomes longer in the display device.
This is due to the time constant of the time constant circuit. That is, for securely decreasing the rush current, it is necessary to attenuate the gate voltage gradually by increasing the time constant. As a result, the starting timing of the FET is delayed. Inversely, for making the starting timing of the FET faster, it is necessary to attenuate the gate voltage steeply by making the time constant small. As a result, the rush current cannot be decreased sufficiently.
It is therefore an exemplary object of the present invention to provide a time constant circuit and the like, which can acquire the characteristic of the output voltage that gradually attenuates after attenuating steeply, compared to the characteristic of the output voltage that only attenuates monotonously.